Flexible and Reconfigurable Implementation of Link Adaptation Algorithms

Reconfigurable systems using FPGAs are of growing interest for the design and implementation of software defined radio transceivers. By reconfiguring a FPGA, its hardware resources can be reused and shared to provide multiple functionalities on a single device. This paper investigates power savings by means of partial reconfiguration for implementing two link adaptation algorithms. These algorithms provide variable performance in terms of spectral efficiency and hardware utilization at different average SNRs. In order to obtain the best tradeoff between i) spectral efficiency and ii) area and power consumption, we propose an efficient implementation that switches between the two algorithms by means of partial reconfiguration. Our experimental results show that our implementation provides a high spectral efficiency and, for certain SNR regions, reduces the hardware resources and thereby the power consumption. Keywords—FPGA, Reconfiguration, Link Adaptation. Abbreviations: BER: Bit Error Rate; CLB: Configurable Logic Block; DSP: Digital Signal Processor; E2R: End-to-End Reconfigurability; FPGA: Field Programmable Gate Array; HIPERLAN: High PERformance Local Area Network; LA: Link Adaptation; OFDM: Orthogonal Frequency Division Multiplexing; PR: Partial Reconfiguration; QAM: Quadrature Amplitude Modulation; RSSI: Received Signal Strength Indication; SAMPDA: Subcarrier based Adaptive Modulation and Power Distribution Algorithm; SDR: Software Defined Radio; SNR: Signal to Noise Ratio; SR: Software Radio; SRA: Simple Rate Adaptive algorithm